A. Field of the Invention
The present invention relates to a method and circuit for biasing transistors to increase performance. The disclosed method and circuit are applicable to boosting performance of a critical path in a larger circuit upon the occurrence of a triggering event.
B. Description of the Related Art
Due to the so-called body effect, which is known to those skilled in the integrated-circuit art, the threshold voltage VT of a transistor, for example a metal oxide semiconductor field effect transistor (MOSFET), can be modified by applying a bias voltage to the substrate. For example, a negative substrate bias relative to a source terminal raises the threshold voltage of an n-type MOSFET (NMOSFET) by reverse-biasing the source-substrate junction, while a slightly positive substrate bias relative to a source terminal reduces the threshold voltage of an NMOSFET by forward-biasing the source-substrate junction. Such biasing of opposite polarities is equally applicable to p-type MOSFETs (PMOSFET) as well, as will be appreciated by those in the integrated circuit art. The change in the threshold voltage VT is typically less than the absolute value of the substrate bias for transistors biased in such a manner. Depending on the structure of the transistor in question, the substrate may also be referred to as the body or replaced by the well of the transistor.
Since ION, the turned-on saturation current of a MOSFET, is proportional to (VDDxe2x88x92VT)2, where VDD is the drain voltage, a reduction in VT is highly effective in boosting ION which improves circuit speed. This way of increasing transistor speed is especially useful in low-voltage circuits, for example where VDD is 1.5 volts or less. A drawback to forward-biasing the source-body junction to lower VT is a greater leakage current through the junction.
FIG. 1 shows a conventional way of lowering VT in an NMOSFET 10 having a source 20 tied to ground. A p-type body 30 is biased with a body voltage Vb derived from a gate 40. A drain 50 is connected to VDD (not shown). Though a wire is shown connecting the gate and body in FIG. 1, depending on the desired level for VT, a voltage divider (not shown) may also be used between the gate and body to generate the desired body voltage Vb. In any event, Vb is conventionally generated from the voltages already available on the chip, such as the gate voltage or VDD.
Also known is a method of accelerating processing in a circuit path using the above conventional transistor biasing. Normally, the circuit path is known and consists of a number of transistors, gates or chips. As explained above, biased transistors have an associated leakage current, and thus use more power than necessary. Therefore, it is good design practice only to bias the transistors for speed when speed is actually needed. Typically, a sensing circuit senses when a signal is propagating toward the circuit path. This sensing circuit will trigger a switching circuit to forward-bias the transistors in the circuit path for maximum performance when the propagating signal arrives.
FIG. 2 illustrates a circuit layout for accomplishing the above-described conventional scheme. A circuit 60 includes a plurality of transistors T1 to TN, whose sources are all tied to VSS (ground). The respective bodies of transistors T1 to TN are tied to a common line emanating from a switching circuit 70. This switching circuit switches the common line between VSS and a bias potential Vb generated by a bias potential generation circuit 80. In FIG. 2, where the transistors are n-type and VSS is ground, Vb would be a positive voltage in order to forward bias the source-body junction. Switching circuit 70 is controlled by standby detection circuit 90, which is triggered by some event to switch the transistors T1 to TN out of standby mode (VSS applied), and into a biased state in preparation for signal propagation.
Accordingly, the present invention is directed to a method and apparatus for biasing transistors that substantially obviates one or more of the problems due to the limitations and disadvantages of the related art.
Advantages of the present invention include a greater reduction in threshold voltage for a given biasing voltage than conventional biasing. Additional features and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the written description and claims hereof, as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention comprises an integrated circuit, including: a transistor having a source and a substrate with a junction therebetween, a bias voltage generator coupled to the source, and the substrate being one of connected and connectable to a predetermined voltage source, wherein the junction between the source and the substrate is forward biased when a bias voltage generated by the bias voltage generator is coupled to the source and the substrate is connected to the predetermined voltage.
Further in accordance with the invention, there is provided a method of increasing the speed of a circuit, which includes at least one transistor having a source and a substrate, the circuit being powered by a first supply voltage and a second supply voltage, the method including: providing a bias voltage having a level outside a voltage range defined by the first supply voltage and the second supply voltage, connecting the first supply voltage to the substrate of the transistor, and connecting the bias voltage to the source of the transistor.
Further in accordance with the invention, there is provided an integrated circuit including: a first supply voltage node and a second supply voltage node, a first gate powered by the first and second supply voltage nodes, a second gate powered by the first and second supply voltage nodes and a bias voltage node such that the second gate functions faster than the first gate, the second gate being coupled to an output of the first gate, and a level shifter connected between the first and second gates, to shift a level of the output of the first gate so that it can effectively operate the second gate.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several embodiments of the invention and together with the description, serve to explain the principles of the invention.